Inside the chip

Inside the 6502

Fly round a diagram of the chip while this project's core runs a program through it. Pick a stop to visit a part, or drag to turn, scroll to zoom and right-drag to move.

The tour1 of 8

The 6502 in outline: the instruction decoder across the top, the control logic under it, and the registers and the arithmetic unit along the bottom, with a pad for each of the package’s 40 pins around the edge. Press play to watch this project’s core run a program through it, one bus cycle at a time.
Every cycle the 6502 puts an address on its 16 address pins and moves one byte over its 8 data pins, in or out. A lit address pad is a 1 on that line. R/W says which way the byte goes, and SYNC lights on the cycle that fetches an instruction.
On the real chip this is a grid of transistors that turns the opcode byte into the signals each step of an instruction needs. Here it lights on the cycle the opcode is fetched.
The logic that sequences each instruction cycle by cycle, with the timing block that splits the clock into two phases. It pulses on every cycle of the trace.
Each column is a register, one cell per bit, bit 7 at the top. A cell is lit for a 1. When an instruction changes a register, its column flashes. The registers show the core’s state when each instruction finishes, not the chip’s internal timing within it.
The ALU adds, subtracts and does the logic operations. It lights while an instruction that computes a result is in progress, such as ADC, AND or INC. On the real chip it also works out indexed addresses and branch targets, which this view does not show.
Eight bits, N V - B D I Z C, set by the results of instructions: negative, overflow, break, decimal, interrupt disable, zero and carry. The program here turns decimal mode on and off on every lap.
Wires from the address bus registers fan out to the address pins, and the data latch connects to the data pins. Each cycle a pulse runs along the wires that changed, inward for a read and outward for a write.

Speed

Cycle

the core, cycle by cycle

Diagram, not the die. The parts are laid out after the 6502's floorplan, but their sizes and places are approximate, nothing is traced from a photograph of the chip, and the pads are drawn in the order of the package's pins. Every value it shows is recorded from this project's core: 562 bus cycles, 176 instructions and 8 laps of the speed check's program, replayed in a loop.

The 3D view needs WebGL, which this browser has not started. The tour above reads the same without it.